Owing to their high integration density, extremely low quiescent leakage current and ever improving power handling capacity, power MOSFETs continue their popular adoption in power electronics such as switching power supplies and converters. Some of the highly important attributes of power MOSFETs are their continuously increasing degree of integration, shrinking package size and accompanying increased required heat dissipation driven by the consumer market.
The following lists some relevant prior arts already reviewed by U.S. application Ser. No. 12/326,065:
“DirectFET” approach (U.S. Pat. No. 6,624,522, U.S. Pat. No. 7,285,866 and U.S. Patent Application Publication 2007/0284722)
U.S. Pat. No. 6,777,800 entitled “Semiconductor die package including drain clip”
Commonly assigned U.S. application Ser. No. 11/799,467 entitled “SEMICONDUCTOR PACKAGE HAVING DIMPLED PLATE INTERCONNECTIONS”
U.S. Pat. No. 6,249,041 entitled “IC chip package with directly connected leads”
U.S. Pat. No. 4,935,803 entitled “Self-centering electrode for power devices”
Commonly assigned US Patent Application Publication 20080087992 entitled “Semiconductor package having a bridged plate interconnection”
Commonly assigned U.S. patent application Ser. No. 12/130,663 entitled “CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE”
Commonly assigned U.S. patent application Ser. No. 12/237,953 entitled “Top Exposed Clip with Window Array”
In a paper entitled “System in Package with Mounted Capacitor for Reduced Parasitic Inductance in Voltage Regulators” by T. Hashimoto et al, published in IEEE Proceedings of the 20th International Symposium on Power Semiconductor Devices & IC's, May 18-22, 2008 Orlando, Fla. pp. 315-318, a developed system in package (SiP) is described on which an input capacitor is mounted for voltage regulators (VR). For convenience of description, this paper is referred to hereinafter as “IEEE paper”. A one-phase VR circuit including parasitic inductance (Ls1-Ls6) and an SiP, which has high-side and low-side MOSFETs and a driver IC, of the IEEE paper is reproduced here as FIG. 1. Correspondingly, two schematic cross-sections of SiPs on a printed circuit board (PCB) are reproduced in FIG. 1A and FIG. 1B.
In the SiP shown in FIG. 1A, the input capacitor is mounted on the PCB, and the MOSFETs are bonded to the lead frames with Cu leads. The calculated parasitic inductance of the SiP is 0.87 nH due to the parasitic inductances from Cin to the SiP (Ls1 and Ls6 shown in FIG. 1). In the improved SiP with a mounted input capacitor of FIG. 1B, the parasitic inductance is reduced by more than 50% (from 0.87 to 0.39 nH) because of a small loop from Cin to the SiP. The upper electrodes of MOSFETs (i.e. drain electrode of the high-side MOSFET and source electrode of the low-side MOSFET) are connected to the lead frames with Cu leads, on which Cin is mounted. High-side and low-side MOSFETs are mounted on the same lead frame, which connects to the output inductor. The high-side MOSFET die is flipped so that its drain electrode faces up, facilitating connection of the drain electrode to the positive terminal of Cin. Another advantage of the improved SiP of FIG. 1B comes from its lower equivalent series resistance (ESR) of the mounted capacitor that enables the reduction of capacitor loss from its resonant current.
Thus, the packaging concept as presented in the IEEE paper is based upon using FLIP-CHIP of standard BOTTOM DRAIN MOSFET dies. Copper leads are used for connecting the top of the MOSFET dies to lead frames. From the photograph of the IEEE paper, the construction details on how the Input Capacitor Cin is mounted on top of the SiP are limited although there is no evidence that the SiP is top exposed outside of the small contact openings made for Cin to increase top-side heat dissipation. Another observation is that the SiP of the IEEE paper does not top expose large areas above the High-side and Low-side MOSFET dies other than the ends of Cin.
In view of the above described prior arts, therefore, it remains highly desirable to further reduce the size of power semiconductor device SiP with an integrated input capacitor while reducing its packaging parasitic inductance and resistance, reducing ESR of its input capacitor and lowering its packaging thermal resistance.